Inside The Largest Humanoid Robot Data Factory In The United States

Meet Sonny. Inside the warehouse that made the sailcloth for the USS Constitution, this vaguely humanoid robot is part of an attempt at reinventing work.

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Apple considering Intel and Samsung for US chip production, report claims — consumer electronics giant looks to diversify supply chain amid chip shortages

Apple is reportedly in early talks with Intel and Samsung to secure more production for its advanced chips, as the company is constrained by the limited availability of advanced nodes that its SoCs are produced on.
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China pushes for 70% homegrown silicon wafer use as domestic firm ramps up 12-inch production — government seeking to localize critical chip supply chain amid AI boom and export restrictions

China is targeting 70% local wafer sourcing as firms like Eswin scale 12-inch production, aiming to reduce reliance on foreign suppliers and support growing AI chip demand.
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ASML’s roadmap for chipmaking lithography tools examined — from DUV to Low-NA, High-NA, Hyper-NA, and beyond

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.
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Intel details 18A-P process node, touts higher performance, lower power, and better thermals — 9% more performance, thermal conductivity improved by 50%

Intel details improvements of 18A-P that include higher performance, lower power, reduced variability, improved yields, and more.
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1X Kicks Off Full-Scale Production Of Humanoid Robot Neo

Are we nearing the tipping point for humanoid robots? We actually might, given that 1X just hit full-scale manufacturing of Neo.

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TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu’s Monaka CPU to benefit from face-to-face chiplet stacking

TSMC adds support for face-to-face stacking, 6.5 µm and 4.5 µm pitches for the next generation of SoIC 3D stacking.
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Inside Google’s TPU V8 strategy, delivering two chips for two crucial tasks at incredible scale — network scales up to 1 million TPUs per cluster, an advantage over Nvidia AI accelerators

Google announced its eighth-gen TPUs at Cloud Next, shipping two distinct chip designs for the first time in the TPU program’s decade-long history.
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TSMC’s details next-gen CoWoS roadmap: over 14-reticle packages and 48x leap in compute power expected by 2029 — massive size enables 24 HBM5E stacks and additional memory bandwidth jump

TSMC claims that CoWoS innovations will enable 48x more compute and 34x more memory bandwidth for 2029 AI processors.
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Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute

Bolt Graphics has announced its completed tape-out of a test chip for its Zeus GPU, marking the startup’s first move from FPGA emulation to manufactured silicon.
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